Friday, June 20, 2014

High-integrity interface for mass interconnect systems!

A new JTAG*/boundary-scan hardware interface is now available for the Peak Group's production family of PXI test systems. The JT 2147/VPC from JTAG Technologies is a signal-conditional module that allows “ideal world” connections from JTAG Technologies PXI and PXIe DataBlaster high-speed boundary-scan controllers to the VPC (Virginia Panel Corporation) mass interconnect system supplied and used in Peak’s configurable PXI-based functional testers.

Based on the highly successful QuadPod(TM) architecture from JTAG Technologies, the JT 2147/VPC has been specifically designed for connection into VPC’s G20x or G14x 192-pin ‘QuadraPaddle’ connectors, and is fully compatible with the Peak system design.

The JT2147/VPC features four independent JTAG test access ports (TAPs) along with 16 static DIO (digital input/output) channels and 64 dynamic DIOS (digital input/output scan) channels. Adding boundary-scan capabilities to any board or system tester will increase fault coverage of interconnections, logic parts and in-signal passives. It will also frequently reduce fixture costs due to test-point reduction and will allow in-system programming of memories and programmable logic parts.

JTAG/boundary-scan applications prepared using JTAG Technologies ProVision ATPG software tools may be executed on the PXI platform with driver packages that are available for NI LabView, TestStand and LabWindows alongside Geotest ATEasy and a number of generic language compilers including .NET framework, C++ and VB.

The VPC adaptors utilise standard QuadraPaddle connector modules, providing a wide variety of contact types. The connection between the PXI instrument and receiver module is accomplished using a passive printed circuit board, an active signal-conditioning module (as with the JT 2147/VPC) or a flexible circuit, with each providing optimum connectivity performance while reducing wiring cost.

*JTAG - Joint Test Action Group, the common name for the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture.

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